The Layout Problem

Astrus does layout on the microchip level (vs the PCB level). Layout on the microchip level is significantly more difficult and takes much more time than layout on the PCB level.

Within microchip design, there is two key categories of design work, Digital and Analog. Digital layout is currently almost entirely automated. For analog layout, the process is still completely manual. This job is done by layout engineers.

Every microchip will have both an analog and digital portion, but for most chips with analog design takes longer than the digital design.

https://semiengineering.com/mixed-messages-for-mixed-signal/

At Astrus we are tackling analog layout, which represents the majority of the design time for most chips.

The current design process included two key roles:

1) First a circuit designer will design an idealized version of the circuit, called a schematic.

2) Then a layout engineer will do layout, the process of placing components and routing wires using CAD tools.

To layout a common circuit like an op amp, it will take a layout engineer anywhere from 6-20 hours to complete. It is essentially a simple puzzle they are trying to solve. How to place the components and route the wires in a way that meets the requirements. Layout is also an iterative process, once the layout engineer finishes the layout, the analog circuit designer has to re-simulate the circuit. It usually takes around 5 iterations to get correct.

Given the time it takes layout engineers to complete a layout, and the number of iterations required, it can take some circuits weeks to complete.

To put this in perspective, one of Intels design teams, responsible for a subcomponent in a microchip, will spend an entire year of this back and forth process between circuit designers and layout engineers to complete their designs. That team has 50 circuit engineers and 50 layout engineers, and they all work in this 1:1 fashion iterating on designs.

The layout problem is also increasing in complexity as transistors get smaller.

There are two primary reasons for the increase in difficulty:

1) DRC complexity: The manufacturing rules (called Design Rule Check, DRC) is increasing as we approach smaller transistor sizes. This means layout engineers spend much more time tweaking the designs to make them compliant with the DRC rules. More on DRC here.

2) Layout Sensitivity: With smaller transistor sizes, it is more difficult to place and route components in way that also satisfies requirements. Resistance and capacitance requirements become more difficult to achieve.